Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017 PROJECT TITLE :Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017ABSTRACT:The generation of important power droop (PD) throughout at-speed take a look at performed by Logic Designed-In Self Take a look at (LBIST) is a serious concern for trendy ICs. In truth, the PD originated throughout check might delay signal transitions of the circuit underneath check (CUT): an impact that will be erroneously recognized as delay faults, with consequent erroneous generation of take a look at fails and increase in yield loss. In this paper, we propose a unique scalable approach to reduce the PD throughout at-speed check of sequential circuits with scan-based mostly LBIST using the launch-on-capture scheme. This is achieved by reducing the activity issue of the CUT, by proper modification of the take a look at vectors generated by the LBIST of sequential ICs. Our scalable solution permits us to scale back PD to a value almost like that occurring during the CUT in field operation, while not increasing the quantity of take a look at vectors required to attain a target fault coverage (FC). We have a tendency to gift a hardware implementation of our approach that needs limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach permits a important reduction of the number of test vectors (by more than fifty%), thus the take a look at time, to attain a target FC. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression - 2017 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding - 2017
